1. Field of the Invention
The present invention relates generally to optical metrology and more particularly to characterizing and monitoring the intra-field distortions of projection imaging systems used in semiconductor manufacturing.
2. Description of the Related Art
Today""s lithographic processing requires ever tighter layer-to-layer overlay tolerances to meet device performance requirements. Overlay registration is defined as the translational error that exists between features exposed layer to layer in the vertical fabrication process of semiconductor devices on silicon wafers. Other names for overlay registration include, registration error and pattern placement error, and overlay error. Overlay registration on critical layers can directly impact device performance, yield and repeatability. Increasing device densities, decreasing device feature sizes and greater overall device size conspire to make pattern overlay one of the most important performance issues during the semiconductor manufacturing process. The ability to accurately determine correctable and uncorrectable pattern placement error depends on the fundamental techniques and algorithms used to calculate lens distortion, stage error, and reticle error.
A typical microelectronic device or circuit may consist of 20-30 levels or pattern layers. The placement of pattern features on a given level must match the placement of corresponding features on other levels, i.e., overlap, within an accuracy which is some fraction of the minimum feature size or critical dimension (CD). Overlay error is typically, although not exclusively, measured with a metrology tool appropriately called an overlay tool using several techniques. See for example, Semiconductor Pattern Overlay, N. Sullivan, SPIE Critical Reviews Vol. CR52, 160:188. The term overlay metrology tool or overlay tool means any tool capable of determining the relative position of two pattern features or alignment attributes, that are separated within 500 um (microns) of each other. The importance of overlay error and its impact to yield can be found elsewhere. See Measuring Fab Overlay Programs, R. Martin, X. Chen, I. Goldberger, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, 64:71, March, 1999; New Approach to Correlating Overlay and Yield, M. Preil, J. McCormack, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, 208:216, March, 1999.
Lithographers have created statistical computer algorithms (for example, Klass II and Monolith) that attempt to quantify and divide overlay error into repeatable or systematic and non-repeatable or random effects. See Matching of Multiple Wafer Steppers for 0.35 micron Lithography using advanced optimization schemes, M. van den Brink, et. Al., SPIE VOL. 1926, 188:207, 1993; A Computer Aided Engineering Workstation for registration control, E. McFadden, C. Ausschnitt, SPIE Vol. 1087, 255:266, 1989; Semiconductor Pattern Overlay, supra; Machine Models and Registration, T. Zavecz, SPIE Critical Reviews Vol. CR52, 134:159. An overall theoretical review of overlay modeling can be found in Semiconductor Pattern Overlay, supra.
Overlay error is typically divided into the following two major categories. The first category, inter-field or grid overlay error, is concerned with the actual position of the overall device pattern imaged into the photoresist on a silicon wafer using an exposure tool, i.e., stepper or scanner as referenced from the nominal center of the wafer, see FIG. 18.
Obviously, the alignment of the device pattern on the silicon wafer depends on the accuracy of the stepper or scanner wafer handling stage or wafer stage. Overlay modeling algorithms typically divide inter-field or grid error into five sub-categories or components, each named for a particular effect: translation, rotation, magnification or scale (in both x and y directions), non-orthogonality, and residuals. See A Computer Aided Engineering Workstation for registration control, supra.
The second category, intra-field overlay error, is the positional offset of an individual point inside a field referenced to the nominal center of an individual exposure field, as illustrated in FIG. 19. The term xe2x80x9cnominal centerxe2x80x9d means the exact location of the center of a xe2x80x9cperfectlyxe2x80x9d aligned exposure field; this is the same as the requested field center coordinates given to the lithography tool when it is programmed for the job. Intra-field overlay errors are generally related to lens aberrations, scanning irregularities, and reticle alignment. Four sub-categories or components of intra-field overlay error include: translation, rotation, magnification and lens distortion. It is common practice to make certain assumptions concerning the magnitude and interaction of stage error and lens distortion error in modern overlay algorithms that calculate lens distortion. The common rule is: xe2x80x9ctrust the accuracy of the stage during the creation of the overlay targets by making the simple assumption that only a small amount of stage error is introduced and can be accounted for statisticallyxe2x80x9d. See A xe2x80x9cgolden standardxe2x80x9d wafer design for optical stepper characterization, K. Kenp, C. King, W. W, C. Stager, SPIE Vol. 1464, 260:266, 1991; Matching Performance for multiple wafer steppers using an advanced metrology procedure, M. Van den Brink, et. Al., SPIE Vol. 921, 180:197, 1988.
It is important for this discussion to realize that most overlay measurements are made on silicon product wafers after each photolithographic process, prior to final etch. Product wafers cannot be etched until the resist target patterns are properly aligned to the underlying target patterns. See Super Sparse overlay sampling plans: An evaluation of Methods and Algorithms for Optimizing overlay quality control and Metrology tool Throughput, J. Pellegrini, SPIE Vol. 3677, 72:82, 36220. Manufacturing facilities rely heavily on exposure tool alignment and calibration procedures. See Stepper Matching for Optimum line performance, T. Dooly, Y. Yang, SPIE Vol. 3051, 426:432, 1997; Mix-And-Match: A necessary Choice, R. DeJule, Semiconductor International, 66:76, Feb, 2000; Matching Performance for multiple wafer steppers using an advanced metrology procedure, supra, to help insure that the stepper or scanner tools are aligning properly; inaccurate overlay modeling algorithms can corrupt the exposure tool calibration procedures and degrade the alignment accuracy of the exposure tool system. See Super Sparse overlay sampling plans: An evaluation of Methods and Algorithms for Optimizing overlay quality control and Metrology tool Throughput, supra.
Over the past 30 years the microelectronics industry has experienced dramatic rapid decreases in critical dimension by moving constantly improving photolithographic imaging systems. Today, these photolithographic systems are pushed to performance limits. As the critical dimensions of semiconductor devices approach 50 nm the overlay error requirements will soon approach atomic dimensions. See Life Beyond Mix-and-Match: Controlling Sub-0.18 micron Overlay Errors, T. Zavecz, Semiconductor International, July, 2000. To meet the needs of next generation device specifications new overlay methodologies will need to be developed. In particular, overlay methodologies that can accurately separate out systematic and random effects and break them into assignable causes will greatly improve device process yields. See A New Approach to Correlating Overlay and Yield, supra.
In particular, those new overlay methodologies that can be implemented into advanced process control or automated control loops will be most important. See Comparisons of Six Different Intra-field Control Paradigms in an advanced mix and match environment, J. Pellegrini, SPIE Vol. 3050, 398:406, 1997; Characterizing overlay registration of concentric 5xc3x97 and 1xc3x97 stepper Exposure Fields using Inter-field Data, F. Goodwin, J. Pellegrini, SPIE Vol. 3050, 407:417, 1997. Finally, another area where quantifying lens distortion error is of vital concern is in the production of photomasks or reticles during the electron beam manufacturing process. See Handbook of Microlithography and Microfabrication Vol. 1 P. Rai- Choudhury 1997 pg. 417.
Semiconductor manufacturing facilities generally use some version of the following complex overlay procedure to help determine the magnitude of lens distortion independent of other sources of systematic overlay error. The technique has been simplified for illustration. See Analysis of image field placement deviations of a 5xc3x97 microlithographic reduction lens, D. MacMillen, et. Al., SPIE Vol. 334, 78:89, 1982. FIGS. 2 and 3 show typical sets of overlay targets 300, includingxe2x80x94one large or outer box 302 and one small or inner target box 304. FIG. 1 shows a typical portion of a distortion test reticle 102 used in the prior art. It should be noted that the chrome target patterns on most reticles are 4 or 5 times larger as compared with the patterns they produce at the image plane; this simply means modern steppers are reduction systems. Further, for purposes of discussion, it is assumed that the reticle pattern is geometrically perfect, (in practice, the absolute positions of features on the reticle can be measured and the resulting errors subtracted off). First, a wafer covered with photoresist is loaded onto the wafer stage and globally aligned. Next, the full-field image of the reticle, 102 in FIG. 1 is exposed onto the resist-coated wafer 2102 in FIG. 21. For purposes of illustration, we assume that the distortion test reticle consists of a 5xc3x975 array of outer boxes evenly spaced a distance M*P, across the reticle surface see FIG. 1. It is typically assumed that the center of the optical system is virtually aberration free. See Analysis of image field placement deviations of a 5xc3x97 microlithographic reduction lens, supra. With this assumption, the reticle, 102 in FIG. 1 is now partially covered using the reticle blades, 1704 in FIG. 17, in such a way that only a single target at the center of the reticle field, box 104, in FIG. 1, is available for exposure. Next, the wafer stage is moved in such a way as to align the center of the reticle pattern directly over the upper left hand corner of the printed 5xc3x975 outer box array, wafer position 2106, FIG. 21. The stepper then exposes the image of the small target box onto the resist-coated wafer. If the stepper stage and optical system were truly perfect then the image of the small target box would fit perfectly inside the image of the larger target box, as illustrated in FIGS. 4 and 21, from the previous exposure.
At this point the stepper and wafer stage are programmed to step and expose the small target box in the 5xc3x975 array where each exposure is separated from the previous one by the stepping distance P. With the assumption of a perfect stage, the final coordinates of the small target boxes are assumed to form a perfect grid, where the spacing of the grid is equal to the programmed stepping distance, P. Finally, if the first full-field exposure truly formed a perfect image, then the entire 5xc3x975 array of smaller target boxes would fit perfectly inside the 5xc3x975 array of larger target boxes as illustrated in FIG. 4A. Since the first full-field exposure pattern is in fact distorted due to an imperfect imaging system the actual position of the larger target box will be displaced relative to the smaller target boxes for example, as shown in FIG. 31. The wafer is then sent through the final few steps of the photographic process to create the final resist patterned overlay targets. The overlay error at each field position, see FIGS. 28, 29, and 30, can be measured with a standard optical overlay tool and displayed in vector notation see FIGS. 28-30. Using the models described below (eq1 and eq2) the overlay data are analyzed, and the lens distortion error is calculated.
The following inter-field and intra-field modeling equations are commonly used to fit the overlay data using a least square regression technique. See Analysis of image field placement deviations of a 5xc3x97 microlithographic reduction lens, supra.
dxf(xf,yf)=Tx+s*xfxe2x88x92q*yf+t1*xf2+t2*xf*yfxe2x88x92E*(xf3+xf*yf2)xe2x80x83xe2x80x83(eq 1) 
dyf(xf,yf)=Ty+s*yf+q*xf+t2*yf2+t1*xf*yfxe2x88x92E*(yf3+yf*xf2)xe2x80x83xe2x80x83(eq 2) 
where
(xf,yf)=intra-field coordinates
(dxf, dyf)(xf,yf)=intra-field distortion at position (xf, yf)
(Tx, Ty)=(x,y) intra-field translation
s=intra-field overall scale or magnification
q=intra-field rotation
(t1, t2)=intra-field trapezoid error
E=intra-field lens distortion.
A problem with the this technique is two-fold; first, it is standard practice to assume that the wafer stage error is very small, randomly distributed, and can be completely accounted for using a statistical model. See Analysis of image field placement deviations of a 5xc3x97 microlithographic reduction lens, supra; A xe2x80x9cgolden standardxe2x80x9d wafer design for optical stepper characterization, supra; Matching Management of multiple wafer steppers using a stable standard and a matching simulator, supra; Matching Performance for multiple wafer steppers using an advanced metrology procedure, supra. In general, the wafer stage introduces both systematic and random errors, and since the lens distortion is measured only in reference to the lithography tool""s wafer stage, machine to machine wafer stage differences show up as inaccurate lens distortion maps. Secondly, the assumption that lens distortion is zero at the center of the lens is incorrect.
A technique for stage and xe2x80x98artifactxe2x80x99 self-calibration is described in See Self-calibration in two-dimensions: the experiment, M. Takac, J. Ye, M. Raugh, R. Pease, C. Berglund, G. Owen, SPIE Vol. 2725, 130:146, 1996; Error estimation for lattice methods of stage self-calibration, M. Raugh, SPIE. Vol. 3050, 614:625, 1997. It consists of placing a plate (artifact) with a rectangular array of measurable targets on a stage and measuring the absolute positions of the targets using a tool stage and the tool""s image acquisition or alignment system. This measurement process is repeated by reinserting the artifact on the stage but shifted by one target spacing in the X-direction, then repeated again with the artifact inserted on the stage shifted by one target spacing in the Y-direction. Finally, the artifact is inserted at 90-degrees relative to its"" initial orientation and the target positions measured. The resulting tool measurements are a set of (x, y) absolute positions in the tool""s nominal coordinate system. Then, the absolute positions of both targets on the artifact and a mixture of the repeatable and non-repeatable parts of the stage x, y grid error are then determined to within a global translation (Txg, Tyg), rotation (qg) and overall scale ((sxg+syg)/2) factor. This technique is not directly applicable to the present situation since it requires that the measurements be performed on the same machine that is being assessed by this technique. Furthermore, this prior art technique requires measurements made on a tool in absolute coordinates; the metrology tool measures the absolute position of the printed targets relative to it""s own nominal center; so absolute measurements are required over the entire imaging field (typical size greater than xcx9c100 mm{circumflex over ( )}2).
Therefore there is a need for an effective way to determine the lens distortion of a projection system independent of other sources of systematic overlay error.
A projection lens distortion error map is created using standard overlay targets and a special numerical algorithm. A reticle including of a 2-dimensional array of standard overlay targets is exposed several times onto a photoresist coated silicon wafer using a photolithographic stepper or scanner. After exposure, the overlay target patterns are measured for placement error using a conventional overlay metrology tool. The resulting overlay data are then supplied to a software program that generates a lens distortion map for the photolithographic projection system. The technique does not require the use of a special reference wafer in order to obtain a complete set of lens distortion data.
One feature is that the technique is both self-consistent and self-referenced thus making the procedure easy to implement in production environments. Most importantly, the technique determines all lens distortion error excluding total translational, rotational, orthogonality and x and y scale placement errors. In addition, the results are decoupled from the effects of stage, wafer alignment, and reticle alignment error. Decoupling these errors from lens distortion error allows the user to more accurately model other sources of placement error in the lithographic process. The technique can be adjusted for accuracy by simply adjusting the number of measurements or stepping patterns used to create the overlay targets.
One aspect includes exposing and printing a minimum of 4 full-field overlay targets at strategic locations across the wafer. Another aspect includes 6 full-field exposures but determines the lens distortion error to within translation, rotation and overall scale or magnification. Additional aspects allow for further reduction of the effects of overlay metrology tool noise.
The technique forms a methodology that can be modified slightly to achieve varying degrees of overall accuracy. Also, the technique can easily be implemented in a modern semiconductor manufacturing facility. For example, a stepper prints the full field of an overlay target reticle 2002 in FIG. 20, onto a resist coated silicon wafer 2402 in FIG. 24 using four exposures. The exposures occur in pairs labeled X and Y in FIG. 24. One pair of exposures denoted X, 3502, in FIG. 35 consists of a first exposure at some nominal position illustrated by the outline of field in solid line, and a second exposure illustrated by a dotted line, shifted in the X-direction by a distance p+dp as illustrated in FIG. 35B. This results in two overlapped fields as shown in FIGS. 11 and 35B. Another pair of exposures (denoted Y, 3504, in FIG. 35 consists of a first exposure at some nominal position illustrated by the outline of field in solid line and a second exposure illustrated by a dotted line shifted in the Y-direction by a distance p+dp as illustrated in FIG. 35A. This results in two overlapped fields as shown in FIGS. 12 and 35A. The resulting exposure patterns are then developed-out or delineated using a standard photolithographic process. The patterned overlay targets, or printed feature targets illustrated in FIGS. 11, 12, and 27, are then measured using a standard optical metrology tool currently available from commercial vendors such as KLA-Tencor of San Jose [Model 5200, See KLA 5105 overlay brochure, KLA-Tencor; KLA 5200 overlay brochure, KLA-Tencor] or Bio-Rad Semiconductor Systems of Mountain View, Calif. [Model Quaestor Q7, See Quaestor Q7 Brochure, Bio-rad Semiconductor Systems].
Because the technique utilizes a high precision overlay metrology tool for local measurements and extracts the global lens distortion data in a unique way means the metrology error multiplier is kept near unity. In addition, the technique can be used in conjunction with traditional overlay techniques to better understand, model and correct pattern placement errors. Additional applications of the above outlined procedure include: improved lithographic simulation using conventional optical modeling software, advanced process control in the form of feedback loops that automatically adjust the projection lens for optimum performance, and reticle correction algorithms that compensate for lens aberration. The technique forms a self-referenced methodology that does not require a special set of overlay calibration wafers or assumptions concerning the placement accuracy of the stage.